MemoryCycleMethod Enum

Accurate

Memory read cycles (MREQ + RD) last for two T-States. Memory write cycles (MREQ + MW) last for one cycle, on the second cycle. (Because first is just MREQ, no MW)

End

Memory read (MREQ + RD) and write (MREQ + MW) cycles last for one T-State on the second T-State.

Start

Memory read (MREQ + RD) and write (MREQ + MW) cycles last for one T-State on the first T-State.