Z80NPins Enum

Definition

Describes the Z80N bus control pins asserted during a T-state, sampled at the rising edge of the T-state's clock. Active-low pins are represented as active-high flags.

public enum Z80NPins

Fields

Name	Description
HALT	The CPU has executed a HALT instruction and is awaiting an interrupt.
IORQ	Input/output request; the address bus holds a valid I/O port address, or the CPU is acknowledging an interrupt when combined with M1.
M1	Machine cycle one; the CPU is fetching an opcode, or acknowledging an interrupt when combined with IORQ.
MREQ	Memory request; the address bus holds a valid memory address.
NEXTREG	Next register write; the low byte of the address bus holds the number of the Next register to write to and the data bus holds the value to write to it.
None	No pins are asserted.
RD	Read; the CPU wants to read data from memory or an I/O port.
RFSH	Refresh; the address bus holds a refresh address for dynamic memory.
WR	Write; the data bus holds valid data to write to memory or an I/O port.